1. Technical Field
The invention relates to systems and methods for testing circuits. In particular, the invention relates to systems and methods for testing very large scale integrated (VLSI) circuits.
2. Related Art
VLSI circuits typically include hundreds of thousands or millions of transistors on a single integrated circuit. The VLSI circuits may be tested for physical defects, such as those introduced by imperfections in the manufacturing process or aging of the devices. However, the very high transistor count and circuit density of VLSI circuits make them extremely difficult and expensive to test comprehensively. In particular, sequential circuit testing for VLSI circuits is considered impractical due to computational complexity of the sequential test pattern generation, necessitating design for testability (DFT) techniques to test the VLSI circuit. One type of DFT technique is serial-scan, whereby the storage elements in a circuit can be reconfigured for serial shift in and out operation to attain the desired controllability and observability with relatively low hardware overhead.
Serial scan requires that the storage elements (e.g., flip flops or FFs) in the circuit use specially designed scan-cell flip flops (SSC) that are connected to form a serial shift-register (or a collection of shift registers) during test mode (as shown in FIG. 1b). FIG. 1a shows an example of a serial-scan cell (SSC). The serial scan-cell includes a flip flop 100 and multiplexor 102. Because the serial-scan cell is a multiplexer based design, the multiplexor at the input of each flip-flop selects between the combinational path in normal mode (e.g., non-test mode) and the output of the previous flip-flop in test mode, as shown in FIG. 1a. An example serial scan implementation is shown in FIG. 1b. During normal mode, the flip-flops capture the normal data from the combinational logic circuit. When test mode is selected, each flip-flop receives its input from the previous flip-flop in the scan chain and feeds the next flip flop. Once the states of the flip-flops are set by the scan-in operation (see “Scan In” in FIG. 1b), normal mode may be selected and the next state data may be captured by toggling the clock. Captured data may be scanned out (see “Scan Out” in FIG. 1b) by switching back to test mode.
As shown in FIGS. 1a and 1b, serial scan has relatively low hardware overhead, including scan routing, test mode signal routing, and additional gates for each flip-flop. Thus, serial scan has been accepted by the industry due to its ability to provide high fault coverage and ease of test generation. However, serial scan suffers from several problems. First, serial scan causes higher switching activity in the circuit which in turn results into higher power consumption during the scan operation than during normal operation. The voltage droop and excessive heat dissipation caused by the high power consumption during testing may produce incorrect responses even for circuits with no actual defects. Further, the high heat dissipation may damage the circuit under test, resulting in yield loss. Second, serial scan has a relatively long test application time and a greater test data volume due to the serial nature of the scan. Specifically, for any performed test (even for a test that only requires a small fraction of the scan cells to be set or updated during the test), each test vector and test response must be fully shifted in and out through the entire scan chain.
Several methods have been developed to address the problems of serial scan. One method is random access scan, whereby each storage element in a sequential circuit has a unique address and is individually written or read by addressing it. FIG. 2a shows an example of a random access cell (RAC). As shown in FIG. 2a, the random-access cell includes a flip flop 100 and two multiplexors 200, 202. Multiplexor 200 is for addressing the individual random-access cell using X & Y enable lines. Multiplexor 202 receives as input a mode signal to determine whether the cell is operating in normal or test mode. An example random access scan implementation is shown in FIG. 2b. The random access cell may be individually addressed using the row and column enable decoders. Outputs from the row and column enable decoders may be used to select a single random access cell, as shown in FIG. 2b. Thus, for n number of cells, the random access scan structure allows the reading or writing of any flip-flop in the circuit using log2 n address bits. The address may be applied by either a parallel manner using multiplexed primary inputs or a serial manner using an address shift register.
Because random access scan may individually address the cells, many of the problems associated with serial scan may be overcome. For example, random access scan reduces the test power significantly since the unnecessary switching activity created by scan-shifting is eliminated. Further, the test cost, including test application time and test data volume, is reduced using random access scan. However, random access scan suffers from significantly high hardware overhead as compared to serial scan. In particular, the overhead for each of the individual cells is higher, due to the additional multiplexors, and the overhead for the architecture is higher due to the excessive routing for enable lines and data signal routing.
What is needed is a system and method for testing circuits which overcomes the problems of the prior art.